Most RISC-V silicon you can actually touch still feels like an embedded or edge story: custom BSPs, per-chip OS ports, and a long checklist before you get a boring Ubuntu install. On October 19, 2026, Hangzhou chip designer SpacemiT (进迭时空) stood up at the 2026 RISC-V China Summit in Shenzhen and said that era is ending for servers. Its new Vital Stone V100 is billed as the industry’s first general-purpose compute chip that fully conforms to the RISC-V server specification stack — and it shipped with three whole-server reference platforms on the same day.
That “first / fully conforming” framing is SpacemiT’s claim, echoed in Chinese coverage and picked up by Linux-hardware outlets. There is no independent certification report in our sources to audit the marketing line. What you can inspect is the checklist they say they hit, and whether that checklist matches how you buy x86 or Arm server iron today.
What’s inside the socket
V100 is a 46-core hybrid co-developed with the open-source XiangShan (香山) team: 6× XiangShan Kunminghu V2R2 cores plus 40× SpacemiT X100 cores. Company numbers: Kunminghu tops out at 2.1 GHz with single-core SPECint2006 ≥ 15.0/GHz; X100 reaches 2.4 GHz with ≥ 9.0/GHz. Dual-socket coherent interconnect stretches the platform to 92 cores. The chip targets the RVA23 profile.
Memory and I/O are server-shaped on paper: 8-channel DDR5 (1DPC, mainstream RDIMM, up to about 4800 MT/s, SpacemiT claims peak bandwidth of ~307 GB/s) and up to 52 PCIe 5.0 lanes configurable from x16 down to x1 — enough, SpacemiT says, to hang four or eight AI accelerator cards plus NVMe/SAS/SATA. Linux site Phoronix additionally reports a 12 nm process and ~120 W TDP; those process/TDP figures are not on SpacemiT’s public product page we fetched, so treat them as secondary reporting until SpacemiT confirms them in an English datasheet.
Performance caveats matter. SPECint2006 is a retired suite; the numbers are per-GHz company claims, not full-chip SPECrate results, and nobody has published an independent lab run yet. Relative to current Xeon, EPYC, or leading Arm server silicon, a mid-node 46-core part at DDR5-4800 is not trying to win a FLOPS race — it is trying to look deployable.
The real headline: server-spec software, not another BSP
SpacemiT’s product page and Shenzhen News coverage say V100 implements the RISC-V server stack end-to-end: Server SoC Specification, Server Platform Specification, RVA23, Boot & Runtime Services (BRS), and the RISC-V Security Model. The company says BRS testing passed in full. Named distributions for direct install/boot/run include openEuler, openRuyi, openKylin, Debian, Ubuntu, Fedora, Red Hat, and Rocky.
If that holds up in the field, the change for operators is concrete: you stop treating each RISC-V server chip like a unique embedded port, and you start treating it more like an x86 SKU where one mainstream Linux image is supposed to land across vendors. SpacemiT founder and CEO Chen Zhijian (陈志坚) framed V100 as the company’s step from edge to cloud and as RISC-V entering a “truly deployable, scalable” datacenter market — vendor rhetoric, but aimed at exactly the friction overseas RISC-V watchers complain about.
Illustration: the other half of the pitch — install a stock Linux, then carve agent workloads into Micro-VMs instead of trusting container isolation alone.
Virtualization, RAS, and agent Micro-VMs
For multi-tenant clouds, SpacemiT lists Hypervisor 1.0 (H extension), memory and interrupt virtualization, standard AIA, and IOMMU-based device virt. It claims those virtualization extensions already have upstream Linux support — no custom kernel required. On the reliability side it cites RISC-V RERI RAS coverage across CPU, memory, PCIe, and buses, plus BMC-visible thermal sensors and in-band/out-of-band firmware management.
Security packaging includes a hardware root of trust, secure boot, key and lifecycle management, secure debug, Chinese national crypto algorithms, and a RISC-V-native TEE. For cloud agent workloads — SpacemiT names emerging apps like Muse and Dots — the company pitches on-chip Micro-VMs: container-like resource overhead with VM-grade isolation, aimed at cutting agent escape risk. That is an architecture story for people building agent hosts; it is not a public Micro-VM product you can download from SpacemiT today based on the materials we reviewed.
Three whole servers, including an AI box with Kunlunxin
Alongside the chip, SpacemiT announced three reference systems: C2201 (general compute), G5201 (AI/智算), and S5236 (storage). G5201 takes up to eight full-height, full-length dual-wide accelerator cards; SpacemiT says it has validated domestic accelerators including Kunlunxin M100 (昆仑芯) and supports high-speed RDMA clustering. Partners also get motherboard, firmware, BMC, and hardware reference designs so they are not starting board bring-up from zero.
For overseas readers watching China accel-card stacks, that is the practical signal: RISC-V host + Chinese PCIe AI cards in one reference SKU. For everyone else, it is still a China-market server announcement — not a Newegg listing.
V100 is a just-announced server CPU and reference platform from SpacemiT — not a consumer part, not a cloud instance type you can spin up tonight, and not an independently benchmarked chip. If you track open-ISA datacenters: bookmark the product page, watch for English datasheets, BRS evidence packs, and whether Debian/Ubuntu/Rocky images really install without chip-specific forks. If you build agent hosts: ask SpacemiT (or OEMs using their reference boards) how Micro-VM scheduling shows up in software, and how Kunlunxin M100 (or other PCIe cards you care about) enumerate under a stock kernel. If you buy racks today: keep comparing against Arm and x86 on process node, SPECrate, and supply — V100’s near-term value is ecosystem shape, not beating EPYC on a FLOPS slide.
How to read the announcement
RISC-V International’s CEO Andrea Gallo, speaking in the summit coverage, pushed the broader line that RISC-V is becoming an architecture for intelligent compute in the datacenter. SpacemiT’s V100 is one Chinese vendor’s attempt to make that sentence operational: same Linux story as x86, virt and RAS checkboxes filled, enough PCIe for AI cards, dual-socket headroom, and an open Chengdu/Beijing XiangShan core in the big-core slots.
The honest overseas takeaway is narrower. Spec compliance and stock-distro installs — if verified — remove the worst friction that kept RISC-V out of “real server” conversations. Process node, clocks, and unverified SPECint2006/GHz figures mean this is still an early server SKU, not a drop-in replacement for your current fleet. Watch the first public distro ISOs, the first third-party benchmarks, and whether G5201-class boxes show up outside China with cards you can buy. Until then, V100 is a milestone announcement worth tracking — not a purchase order.